1. Field of Invention
The present invention relates to a manufacturing process of semiconductor integrated circuit. More particularly, the present invention relates to an alignment mark and a photolithography alignment method using the same for eliminating process bias error.
2. Description of Related Art
The complexity of integrated circuit design increases as the integration of the integrated circuit increases, and the critical dimension of the integrated circuit is continually reduced. Since the integrated circuit is formed by overlapping multiple layers of circuit patterns, the alignment accuracy requirement of each layer of circuit pattern is continually higher and harder to achieve. In particular, the gravity of the alignment accuracy problem is increased when a thin film on alignment marks has an asymmetrical profile, which usually results from asymmetrically depositing the thin film or chemical mechanical polishing the thin film.
For a clearer understanding the impact of the asymmetrical profile of a thin film on alignment accuracy for overlapping layers of circuit patterns, a top view of a conventional alignment mark, box-in-box, is shown in FIG. 1. In FIG. 1, a box-in-box alignment mark is formed by the following steps. A square trench 110 is formed in a substrate 100. The border length of the square trench 110 is about 50 μm, and the depth of the square trench 110 is about 0.3-0.6 μm. A thin film is deposited on the substrate 100. Ideally, a smaller square trench 130 will be formed in the center of the square trench 110. Both the geometric centers of the square 110 and 130 are at position C1. However, if the profile of the thin film is asymmetrical, another smaller square trench 140 is formed instead of the square trench 130. The geometric center of the square trench 140 is at position C2, which is displaced from the position C1. Since an alignment target, i.e. the geometric center of the square trench formed by this thin film, is needed when a photolithography process is performed for patterning this thin film, an alignment bias error occurs if the geometric center of the square trench 140 at position C2 is displaced from the ideal geometric center at position C1.
For example, the polishing direction of chemical mechanical polishing is anisotropic, and an asymmetrical profile of a thin film thus results. FIG. 2 shows a cross-sectional view of a thin film having an asymmetrical profile caused by chemical mechanical polishing. A square trench 210 having a geometric center C1 is formed on a substrate 200. A tungsten metal layer is conformally deposited on the substrate 200. Chemical mechanical polishing is performed to remove the tungsten layer higher than the level of the substrate 200 to form a tungsten plug in the integrated circuit regions (not shown in FIG. 2) and tungsten layer 220 in the square trench 210. If the polishing direction is from the right to the left of FIG. 2, the thickness of the tungsten layer at the right hand side (B2) is larger than that at the left hand side (B1). After depositing another layer of metal layer 230, the profile of the metal layer 230 is asymmetrical with respect to the square trench 210. Hence, the geometric center is moved from position C1 to position C2, and the alignment target for patterning the metal layer 230 is at position C2. Thus, an alignment bias error occurs. Another conventional bar-in-bar alignment mark also utilizes the same principle to align layers of circuit patterns. Therefore, similar problems are also encountered.